
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NDMERGE is
    Port ( a : in  STD_LOGIC_VECTOR (15 downto 0);
           ain : in  STD_LOGIC;
           aack : out  STD_LOGIC;
           b : in  STD_LOGIC_VECTOR (15 downto 0);
           bin : in  STD_LOGIC;
           back : out  STD_LOGIC;
           v : out  STD_LOGIC_VECTOR (15 downto 0);
           vstr : out  STD_LOGIC;
           vack : in  STD_LOGIC;
           clkin : in STD_LOGIC);
end NDMERGE;

architecture Behavioral of NDMERGE is

type estados is(juncao, envio);

begin

	dados: process(clkin, ain, bin, vack)
		variable estado: estados := juncao;
		variable vd: STD_LOGIC_VECTOR (15 downto 0);		
	begin
		if clkin'event and clkin = '1' then
			v <= "ZZZZZZZZZZZZZZZZ";
			vstr <= '0';
			aack <= '0';
			back <= '0';
			
			case estado is
			when juncao =>
				if ain = '1' then
					vd := a;
					aack <= '1';
					estado := envio;
				elsif bin = '1' then
					vd := b;
					back <= '1';
					estado := envio;
				end if;
			when envio =>
				if vack = '1' then
					estado := juncao;
				else
					v <= vd;
					vstr <= '1';
				end if;
			end case;
		end if;
	end process dados;

end Behavioral;
